The conventional flip-chip bonding technology is related to dispose a plurality of bumps such as solder balls on an active surface of a chip, then the bumps are electrically and mechanically jointed to the corresponding connection pads of a substrate or a printed circuit board by flipping, attaching, and reflow processes to complete a flip chip assembly. When comparing to the conventional electrical connections of wire bonding, flip chip technologies can be implemented in semiconductor packages with high pin counts to provide shorter electrical connections between bumped chips and substrates with good signal qualities at higher operation frequencies. Traditionally, the solder balls are electrically and mechanically connected to the substrate by reflow processes. However, the solder balls are completely melt under reflow temperature which can not maintain a specific gap between the bumped chip and the substrate, moreover, the solder balls after reflow are spherical with the contour extending outside the corresponding connection pads. To avoid electrical short between the adjacent solder bumps due to bridging and potential contamination issues, a redistribution layer (RDL) has to be designed on an active surface of a chip to change the positions of the solder balls and to increase pitches between solder balls.
Due to the above mentioned issues, IBM (International Business Machines Corporation) implemented metal posts to replace the conventional solder balls without RDL to make the pitch of the metal posts equal to the one of the bonding pads of a chip which is less than 80 μm where soldering materials are implemented for achieving electrical and mechanical connections between the metal posts of the chip and the connection pads of the substrate, i.e., MPS-C2 technology (Metal Post Solder-Chip Connection). During reflow processes, the reflow temperature does not reach the melting point of the metal posts to keep the pillar shape intact without melting into balls. Moreover, the bump pitch of the metal posts can be greatly reduced without bridging issues between the adjacent bumps as the conventional solder balls. Therefore, the bumps can be disposed in a much higher density with smaller pitches without RDL where specific joint heights can be maintained without affecting the filling of underfill materials. This MPS-C2 technology is disclosed in U.S. Pat. No. 6,229,220 B1, entitled “Bump structure, bump forming method and package connection body”
In the MPS-C2 technology, flip-chip die bonder is implemented for fabricating a semiconductor flip-chip assembly by soldering metal posts. As shown in FIG. 1, a substrate 110 has a plurality of bonding fingers 111 disposed on the substrate 110. As shown in FIG. 2, a chip 120 has a plurality of metal posts 121 corresponding to the bonding fingers 111 of the substrate 110 and a component active area 124 located on the center of the active surface of the chip 120 where the metal posts 121 are not disposed inside the component active area 124. Without RDL, the metal posts 121 can be disposed at peripheries of the active surface or any locations except the component active area 124. As shown in FIG. 3, the soldering materials 130 are disposed at the flat tops of the metal posts 121. Through reflow processes, the metal posts 121 are electrically and mechanically connected to the bonding fingers 111 of the substrate 110 by reflowing the soldering materials 130. During flip-chip assembly processes, the metal posts 121 of the chip 120 are aligned to the bonding fingers 111 where the high alignment accuracy is strictly required that the virtual central lines of the bonding fingers 111 can not exceed the edges of the metal posts 121. As shown in FIG. 3, the maximum displacement tolerance between the metal posts 121 and the bonding fingers 111, i.e., the alignment accuracy, can not be greater than half of the width of the bonding fingers 111 which is 25 μm. By using the surface tension of the melt soldering materials 130 under reflowing temperatures, the metal posts 121 still can accurately be aligned to the bonding fingers 111. Therefore, for chips with smaller bump pitches, such as 80 μm pitches or even smaller such as 50 μm pitches, the requirement of alignment accuracy will become higher and tighter. Therefore, in the conventional flip chip technologies, only flip-chip die bonders can achieve the fabrication of flip-chip assembly having MPS-C2 with satisfied yield.
As shown in FIG. 4A, the metal posts 121 are completely aligned to the bonding fingers 111 before reflow processes so that the chip 120 can accurately be connected to the substrate 110 after reflow processes without misalignment issues. As shown in FIG. 4B, with a certain displacement after alignment, the displacement tolerance δ of the chip 120 can not be greater than half of the width, W, of the bonding fingers 111, i.e., δ<½ W, so that the metal posts 121 still can be aligned to the virtual central line of the corresponding bonding fingers 111. During reflow processes, the melt soldering material 130 still has the self-alignment characteristic to pull back and align the displaced metal posts 121 to the corresponding bonding fingers 111 to overcome chip misalignment as shown in FIG. 4C.
However, as shown in FIG. 5, when the displacement tolerance δ of the chip 120 is greater than half of the width, W, of the bonding fingers 111, i.e., δ>½ W, any portions of the metal posts 121 can not be aligned to the virtual central line of the corresponding bonding fingers 111 leading to alignment failure. As shown in FIG. 5B, the soldering materials 130 of the metal posts 121 will be mainly located at the spacing between adjacent bonding fingers 111. Once the soldering materials 130 contact to two adjacent bonding fingers 111, the melt soldering material 130 during reflow processes will not be able to achieve self-alignment of a chip leading to bridging, i.e., electrical short. Or, as shown in FIG. 5C, even though the soldering materials 113 can slightly pull the metal posts 121 back to alignment during reflow processes, however, the metal posts 121 only partially contact to the correct pin positions of the corresponding bonding fingers 111 forming solder joints that can easily be broken. Therefore, when the displacement tolerance δ of the chip 120 is greater than half of the width, W, of the bonding fingers 111, quality of electrical connections as well as the yield of flip-chip assembly are greatly reduced.
As shown in FIG. 6A, before reflow processes, when the displacement tolerance δ of the chip 120 is far greater than half of the width, W, of the bonding fingers 111, reaching one or more pitches of the bonding fingers 111, i.e., the metal posts 121 are aligned to wrong bonding fingers 111. Then, as shown in FIG. 6B, after reflow processes, the metal posts 121 are soldered to wrong bonding fingers 111 causing wrong signal transmission leading to malfunction of the semiconductor flip-chip assembly.
Therefore, in the conventional MPS-C2 technologies, the displacement tolerance δ of a bumped chip ranges from 0 to half of the width W of the bonding fingers, i.e., 0<δ<½ W. Once the displacement tolerance exceeds the above tolerance ranges, the metal posts can not self-align to the corresponding bonding fingers during reflow processes causing tilting or rotation displacement leading to wrong signal transmission where the flip-chip assembled packages have to be reworked or scrapped which greatly impacts the processing yield and cost. Therefore, the conventional MPS-C2 technologies, flip-chip die bonders with bonding accuracy around ±10 μm are required which can be less than half of the width of the bonding fingers such as <50 μm, about 25 μm. The displacement tolerance δ is controlled under 12.5 μm. Moreover, the alignment accuracy of an existing SMT mounter is around ±50 μm which can not reach the flip-chip assembly requirements of MPS-C2 leading to poor qualities of electrical connections with lower assembly yields.